Field
Embodiments of the invention relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.
Background Art
Structures, for example, in which one-time programmable elements are disposed between multiple layer interconnects, and structures in which conventional NAND flash memory is formed in multiple layers by repeated epitaxial formation of silicon films, etc., have been proposed as technology to realize higher memory density without depending on the downscaling of lithography. However, in such methods, the number of lithography steps undesirably increases as the number of stacks increases.
To replace such technology, stacked vertical memory has been proposed (for example, refer to JP-A 2007-266143 (Kokai). In such technology, a memory string made of stacked memory elements is made with one forming by stacking any number of layers of stacked electrodes, collectively making through-holes, forming a memory film including a charge storage layer and the like on the inner walls of the through-holes, and subsequently filling a polysilicon film into the interior. Thereby, a memory can be realized in which the number of lithography steps substantially does not increase even when the number of stacks increases.
Technology also exists to make the semiconductor pillar forming the memory string in a hollow cylindrical configuration to improve the characteristics of the polysilicon channel transistor of such a stacked vertical memory. Thereby, the semiconductor pillar can be formed in a thin film, the effect of states in the polysilicon film can be reduced, and the fluctuation of characteristics of memory cells can be reduced.
However, it is necessary to set the impurity concentration of the source-drain diffusion layer and the channel portion to be relatively high in the case where the semiconductor pillar has a hollow cylindrical configuration with a thin film and a reduced volume. To this end, performing ion implantation from the surface of the stacked structural unit at high acceleration and high currents leads to problems such as longer processing time, increased manufacturing costs, and poor position controllability at deep positions of the stacked structural unit.
Thus, a structure of a high-concentration source-drain diffusion layer having high position controllability while using a hollow cylindrical semiconductor pillar is desired.